One challenge in developing monolithic mixed-signal semiconductor products occurs when designing robust protection circuitry for low-level input pins. Protection may be provided to prevent damage to the low-level input pins from electrical overstress (EOS) events that result from over current or over voltage events that occur while a device is operating. Conventional EOS protection circuitry typically includes clamp circuits extending from an input pin to power supply rails. These clamps, modeled as diode junctions, will shunt excessive input signals to corresponding low impedance power supplies, thus protecting the circuitry from unexpected spikes in the input signals.
FIG. 1 illustrates conventional EOS protection circuitry 100. An input signal IN will be received on an input signal line 110. A first diode D1 will connect the input signal line 110 to a supply voltage and a second diode D2 will connect the input signal line 110 to ground.
Generally a diode will only allow current to flow in a single direction (i.e., when the diode is forward biased), however, diodes do not prevent all the current from flowing in the opposite direction (i.e., when the diode is in a reverse biased state). As seen in FIG. 1, a small amount of leakage current will leak from the supply and ground onto the input signal line.
Under normal operating conditions, the reverse leakage currents of the diodes may exceed the required specification for input leakage/bias current of critical signal pins in the remaining signal chain. For example, for digital X-ray medical imaging, a data acquisition chip is desired that will digitize detector currents from photodiodes/photoconductors on the imaging panel. These detector currents may be in the picoampere range, and conventional clamp circuitry capable of delivering electrostatic discharge (ESD) and latch-up protection to industry-standard levels will not be compatible with the low leakage system needs.
A related difficulty in design is providing an on-chip testing capability for the signal chain. Since the overall system may be complex, it is valuable to have the ability to mimic the input signals normally being delivered to the data acquisition chip. As seen in FIG. 1, a test signal pin 120 may generally be connected to the input signal line 110. If a test signal is applied to the internal signal chain through a multiplexer 125, additional leakage paths can be introduced, and circuit performance during normal operation will be degraded.
Accordingly, there is a need for an electrical overstress protection circuit that minimizes or eliminates the effects of leakage currents introduced onto an input signal line while still providing overstress protection.